Towards a Low-SWaP 1024-beam Digital Array: A 32-beam Sub-system at 5.8 GHz

TL;DR

The paper addresses the need for scalable, low-SWaP digital multibeam beamforming at mmWave by introducing a multiplierless 32-point approximate DFT (ADFT) that enables up to 1024 beams from a 32×32 aperture. The transform is constructed from sparse, integer-coefficient stages, yielding $\hat{\mathbf{F}}_{32}$ with near-DFT performance while requiring zero multiplications and about 348 real additions, and it is factorized into eight sparse matrices for an efficient fast algorithm. Hardware and ASIC results show ~46% area reduction and ~50% faster critical path compared to a fixed FFT, at the cost of roughly 2 dB higher sidelobe levels; the design is implemented with 8-bit inputs and provides real-time beam computation on an FPGA at 120 MHz per beam. The 32-beam sub-system was demonstrated with a 5.8 GHz, 32-element ULA, including RF front-end and ROACH-2-based digital back-end, and validated through measurements that agree well with both exact FFT and ADFT predictions, supporting scalable digital beamspace arrays for mmWave and beyond.

Abstract

Millimeter wave communications require multibeam beamforming in order to utilize wireless channels that suffer from obstructions, path loss, and multi-path effects. Digital multibeam beamforming has maximum degrees of freedom compared to analog phased arrays. However, circuit complexity and power consumption are important constraints for digital multibeam systems. A low-complexity digital computing architecture is proposed for a multiplication-free 32-point linear transform that approximates multiple simultaneous RF beams similar to a discrete Fourier transform (DFT). Arithmetic complexity due to multiplication is reduced from the FFT complexity of $\mathcal{O}(N\: \log N)$ for DFT realizations, down to zero, thus yielding a 46% and 55% reduction in chip area and dynamic power consumption, respectively, for the $N=32$ case considered. The paper describes the proposed 32-point DFT approximation targeting a 1024-beams using a 2D array, and shows the multiplierless approximation and its mapping to a 32-beam sub-system consisting of 5.8 GHz antennas that can be used for generating 1024 digital beams without multiplications. Real-time beam computation is achieved using a Xilinx FPGA at 120 MHz bandwidth per beam. Theoretical beam performance is compared with measured RF patterns from both a fixed-point FFT as well as the proposed multiplier-free algorithm and are in good agreement.

Figures (8)

• Figure 1: (a) Digital beamforming architecture for obtaining $N^2$ beams using an $N \times N$ URA. (b) Block diagram of a $N$-element sub-system that acts as a building block for the $N^2$ rectangular aperture array. The HT block in the figure denotes the Hilbert transform operation.
• Figure 2: The simulated frequency responses of the 32 output bins of the (a) proposed 32-point ADFT, (b) exact DFT; (c) the magnitude error of the two responses.
• Figure 3: Bins that have the highest magnitude error in Fig. \ref{['fig_sim_algo1']}. (c).
• Figure 4: (i) Simulated polar patterns of the 32-beams for a ULA with $\lambda/2$ element spacing. (i-a) Beams corresponding to the ADFT, (i-b) beams obtained with the ideal FFT, and (i-c) the magnitude error between the ADFT and the exact FFT. (ii) Example simulated beam patterns from a Nyquist-spaced URA; (a) $\psi=8.0^{\circ},\phi=-153.4^{\circ}$, (b) $\psi=45.4^{\circ},\phi= -142.1^{\circ}$,(c) $\psi=26.2^{\circ},\phi=45.0^{\circ}$ (the plots are color-coded on a dB scale).
• Figure 5: (a) Overall architecture of the test setup; (b) https://ieeetv.ieee.org/ieeetv-specials/ted-tours-the-brooklyn-5g-summit-expo-floor-3 (starting at 2m:44s in the hyperlinked video); (c) measured S-parameters (return loss and mutual coupling) of the designed antenna array.