Modeling and Predicting Transistor Aging under Workload Dependency using Machine Learning

TL;DR

This work addresses the need for fast, accurate aging models that do not expose confidential foundry parameters by training ML surrogates to replicate physics-based BTI aging under workload-dependent voltage waveforms. It systematically compares SVM, LSTM, and brain-inspired hyperdimensional computing (OnlineHD) as surrogates, using the CARAT framework with SPICE to generate ground-truth traces from a physics model and extrapolate end-of-life delays. Key findings show mean relative errors as low as $1.7\%$ and speedups up to $20\times$ (up to $30\times$ in inference) for HDc, with LSTM offering best full-trace accuracy and SVR providing competitive end-of-life predictions, while HDc offers fast, robust inference and better scalability. The results demonstrate the practicality of ML-based aging models to help circuit designers optimize guardbands and performance without revealing confidential technology details, potentially bridging the gap between foundries and designers on reliability-aided design. Temperature effects and other aging mechanisms remain open directions for extending these surrogates to maintain accuracy across operating conditions.

Abstract

The pivotal issue of reliability is one of colossal concern for circuit designers. The driving force is transistor aging, dependent on operating voltage and workload. At the design time, it is difficult to estimate close-to-the-edge guardbands that keep aging effects during the lifetime at bay. This is because the foundry does not share its calibrated physics-based models, comprised of highly confidential technology and material parameters. However, the unmonitored yet necessary overestimation of degradation amounts to a performance decline, which could be preventable. Furthermore, these physics-based models are exceptionally computationally complex. The costs of modeling millions of individual transistors at design time can be evidently exorbitant. We propose the revolutionizing prospect of a machine learning model trained to replicate the physics-based model, such that no confidential parameters are disclosed. This effectual workaround is fully accessible to circuit designers for the purposes of design optimization. We demonstrate the models' ability to generalize by training on data from one circuit and applying it successfully to a benchmark circuit. The mean relative error is as low as 1.7%, with a speedup of up to 20X. Circuit designers, for the first time ever, will have ease of access to a high-precision aging model, which is paramount for efficient designs. This work is a promising step in the direction of bridging the wide gulf between the foundry and circuit designers.

Figures (12)

• Figure 1: Worst-case models are typically employed in the industry. For transistor aging, they assume constant stress and thus the highest possible degradation (red). Physics-based models are far more accurate because they take the input waveform and recovery effects into account.
• Figure 2: Typically, circuit designers do not have access to accurate physics-based aging models to estimate efficient (i.e., small, yet sufficient) guardbands. *ml-based aging model are free sensitive material and process parameters of the foundry and can thus be shared with designers. Now, circuit designer can create workload-specific aging data for efficient guardbands.
• Figure 3: In the experimental setup, stimuli are applied at circuit level 1 and voltage waveforms for each transistor extracted 2. Those are passed to the aging models 3 to generate the ground truth for the training of the *ml models. Then, their prediction is extrapolated to the *eol 4. Finally, the degradation is applied again at circuit level for efficient guardband estimation 5.
• Figure 4: Voltage waveforms derived from circuit-level stimuli are supplied to the physics-based transistor aging model to create training data for the *ml-based models. Once they are trained, they take voltage waveforms and predict the degradation trace.
• Figure 5: Some history is added to the current input voltage to better capture the voltage dynamics. In this example $h=3$, i.e., the input voltage and $\Delta\text{ V}_{th,i}$ from ti-1, ti-2, and ti-3 are included.