Designing Approximate Arithmetic Circuits with Combined Error Constraints

TL;DR

The paper tackles multi-m metric optimization for approximate arithmetic circuits by extending Cartesian Genetic Programming (CGP) to jointly consider error metrics such as $MAE$, $WCE$, $ER$, $MRE$, $ACC0$, $AVG$, and $Gauss$. It demonstrates that no single metric guarantees global quality, but integrating $ER$ with either $MAE$ or $WCE$ yields the strongest overall trade-offs between power reduction and multiple error criteria, outperforming existing designs like EvoApproxLib. Through extensive CGP runs on 8-bit multipliers, the work provides practical guidance for multi-metric design, showing when error-distribution constraints help or hinder optimization and suggesting that the approach generalizes to other circuits and non-functional metrics. These findings offer a concrete pathway to design energy-efficient approximate circuits that meet complex, application-specific reliability requirements.

Abstract

Approximate circuits trading the power consumption for the quality of results play a key role in the development of energy-aware systems. Designing complex approximate circuits is, however, a very difficult and computationally demanding process. When deploying approximate circuits, various error metrics (e.g., mean average error, worst-case error, error rate), as well as other constraints (e.g., correct multiplication by 0), have to be considered. The state-of-the-art approximation methods typically focus on a single metric which significantly limits the applicability of the resulting circuits. In this paper, we experimentally investigate how various error metrics and their combinations affect the reduction of the power consumption that can be achieved. To this end, we extend evolutionary-driven techniques that allow us to effectively explore the design space of the approximate circuits. We identify principal limitations when complex error constraints are required as well as important correlations among the error metrics enabling the construction of circuits providing the best-known trade-offs between the power reduction and combined error constraints.

Figures (14)

• Figure 1: Comparison of final results for single-objective (CGP) and multi-objective (NSGA-II) approximation methodologies
• Figure 2: The quality of the approximate circuits designed using different error metrics.
• Figure 3: An example of a one-bit full adder encoded using the 1D CGP with parameters: $n_i=3$, $n_o=2$, $n_n=6$, $n_a=2$, $\Gamma=\{\mathrm{inv~(encoded~with~0), and~(1), or~(2), xor~(3)}\}$. The adder is encoded as five active nodes. One node (node 5) is inactive.
• Figure 4: Experimental setup for automated approximation evaluation
• Figure 5: Distribution of relative power if only average error is constrained