Seizure Detection and Prediction by Parallel Memristive Convolutional Neural Networks

TL;DR

This work introduces a parallel memristive CNN architecture for epileptic seizure detection and prediction, achieving state-of-the-art-like accuracy with drastically fewer parameters than conventional CNNs. The system is implemented on analog memristive crossbars, enabling near real-time inference with significantly reduced latency, and is complemented by hardware-aware techniques such as quantization-aware training and a stuck weight offsetting strategy to mitigate non-idealities. Across Bonn, CHB-MIT, and SWEC-ETHZ datasets, the approach demonstrates strong generalization, good robustness to non-idealities, and competitive power-area-latency profiles in a 22 nm CMOS process. The work furnishes a concrete path toward circuit-level realization of edge-enabled seizure detection/prediction, offering practical impact for wearable or implantable neuromorphic medical devices.

Abstract

During the past two decades, epileptic seizure detection and prediction algorithms have evolved rapidly. However, despite significant performance improvements, their hardware implementation using conventional technologies, such as Complementary Metal-Oxide-Semiconductor (CMOS), in power and area-constrained settings remains a challenging task; especially when many recording channels are used. In this paper, we propose a novel low-latency parallel Convolutional Neural Network (CNN) architecture that has between 2-2,800x fewer network parameters compared to SOTA CNN architectures and achieves 5-fold cross validation accuracy of 99.84% for epileptic seizure detection, and 99.01% and 97.54% for epileptic seizure prediction, when evaluated using the University of Bonn Electroencephalogram (EEG), CHB-MIT and SWEC-ETHZ seizure datasets, respectively. We subsequently implement our network onto analog crossbar arrays comprising Resistive Random-Access Memory (RRAM) devices, and provide a comprehensive benchmark by simulating, laying out, and determining hardware requirements of the CNN component of our system. To the best of our knowledge, we are the first to parallelize the execution of convolution layer kernels on separate analog crossbars to enable 2 orders of magnitude reduction in latency compared to SOTA hybrid Memristive-CMOS DL accelerators. Furthermore, we investigate the effects of non-idealities on our system and investigate Quantization Aware Training (QAT) to mitigate the performance degradation due to low ADC/DAC resolution. Finally, we propose a stuck weight offsetting methodology to mitigate performance degradation due to stuck RON/ROFF memristor weights, recovering up to 32% accuracy, without requiring retraining. The CNN component of our platform is estimated to consume approximately 2.791W of power while occupying an area of 31.255mm$^2$ in a 22nm FDSOI CMOS process.

Figures (9)

• Figure 1: An overview of a typical epileptic seizure detection and prediction system. Acquired EEG signals are sampled and processed near-sensor using an AFE, prior to being sent wirelessly to edge device(s) for real-time pre-processing and feature extraction. Features can then be fed into ML and/or DL architectures, residing either on the IoT edge or in the IoT cloud, which perform epileptic seizure detection and prediction.
• Figure 2: A high-level system architecture overview. (a) Raw EEG signals are sampled and digitized using ADC. (b) Features are extracted from sampled EEG signals. (c) Extracted features are fed into a memristive DL accelerator. (d) Accelerator outputs are processed. Fig. \ref{['fig:block_diagram']} depicts the detailed hardware implementation of the accelerator. (e) Processed accelerator outputs are used to determine interictal, preictal, and ictal states. (f) The novel neural network architecture used consists of two parallel 1d-convolutional layers, one average pooling layer, and two fully connected (dense) layers. $N$ is used to denote the batch size, i.e., the number of batches presented to the network in parallel. $f$ denotes the number of filter. $k$ determines the filter size. $s$ denotes the stride length. $p$ denotes the padding. $M$ denotes the number of output neurons for each fully connected layer. Parts of this figure are derived from Lammie2021.
• Figure 3: Architecture hierarchy of our memristive DL accelerator with (a) TDM and (b) Parallelized Implementation.
• Figure 4: Depiction of (a) our adopted overlapped sampling technique extracting $n$ samples from a continuous preictal segment, and (b) the SPH and SOP terms. As can be seen, continuous preictal segments are extracted during the SPH. All preictal samples that occur during the SOP period are discarded.
• Figure 5: A comparison of possible mapping schemes. (a) visualizes the staggering mapping of convolution weights, which is commonly adopted due to its ability to produce all results within a single pass through the crossbar array. (b) visualizes our proposed mapping scheme, without staggering of convolution weights and sparsity in crossbar, at the cost of increased read/write operations. (c) provides a comparison of methods (a) and (b), visualizing when one method should be chosen over the other.