Efficient Quantum Circuit Design with a Standard Cell Approach, with an Application to Neutral Atom Quantum Computers

TL;DR

This work introduces a standard-cell, tile-based framework for quantum circuit design that leverages the regularity of qubit lattices to speed up layout-aware compilation. By using non-configurable 3D standard cells (tiles) and a layout-aware router, the approach yields faster routing, shallower 3D circuits, and concrete resource estimates, demonstrated on cubic Toffoli tiles and a 3D multiplier circuit within neutral-atom hardware models. The method supports co-design with neutral-atom architectures, including zoned memory/processing/measurements and qubit shuttling, and provides exact routing-cost formulas to quantify qubit movement costs. These results point to scalable, regiospecific quantum compilation that can dramatically reduce design time and enable large-scale quantum computations with more predictable resource requirements.

Abstract

We design quantum circuits by using the standard cell approach borrowed from classical circuit design, which can speed-up the layout of circuits with a regular structure. Our standard cells are general and can be used for all types of quantum circuits: error-corrected or not. The standard cell approach enables the formulation of layout-aware routing algorithms. Our method is directly applicable to neutral atom quantum computers supporting qubit shuttling. Such computers enable zoned architectures for memory, processing and measurement, and we design circuits using qubit storages (memory and measurement zones) and standard cells (processing zones). Herein, we use cubic standard cells for Toffoli gates and, starting from a 3D architecture, we design a multiplication circuit. We present evidence that, when compared with automatic routing methods, our layout-aware routers are significantly faster and achieve shallower 3D circuits (by at least 2.5x) and with a lower routing cost. Additionally, our co-design approach can be used to estimate the resources necessary for a quantum computation without using complex compilation methods. We conclude that standard cells, with the support of layout-aware routing, pave the way to very large scale methods for quantum circuit compilation.

Figures (11)

• Figure 1: The standard cell for a 3D implementation of a Toffoli gate: a) Green vertices are the control qubits of the Toffoli gate, and the orange vertex is the target. In the Clifford+T decomposition of the Toffoli gate, the orange and green qubits are CNOT controls and the grey qubits are CNOT targets; b) Pink edges represent SWAPs (routing is discussed in Section \ref{['sec:res']}); c) Reading a circuit from a cell is performed by replacing each vertex with a qubit, and choosing a gate that corresponds to the sticks. Assuming that T and H gates are also executed on the vertices, the circuit from (c) will correspond to Fig. \ref{['fig:tdepth1']} from the Appendix. The red vertex corresponds to the qubit that is targeted by three CNOTs from the Clifford+T decomposition. These cells are not cubes, because they have only seven vertices.
• Figure 2: Quantum circuits are built from cells which are designed specifically for the underlying hardware architecture. In this example, the hardware is organised as a 3D lattice, and the standard cell (blue) might be the one illustrated in Fig. \ref{['fig:cube']}.
• Figure 3: Four tiles (cubic standard cells) and five qubit queues (linear structures) for the 3D layout of a quantum multiplication circuit. The circuit will operate on two registers: $A$ and $B$. The lines of extending out of the figure are queues meant to hold qubits to be used within the multiplier. Specifically, the upper-left queue holds ancillae which will swap with qubits from the $B$ register, the upper right queue holds qubits from the product register, the magenta queue on the bottom holds ancillae which will eventually swap with members of the product register, and the yellow queues going out hold the $B$ operand as well as the designated ancillary qubit $Z$ (the sole grey qubit among the yellow qubits in the queue). These queues are often depicted in abbreviated forms in other figures for the sake of readability, and in fact their form is arbitrary as they will always be chains of qubits.
• Figure 4: SWAP schedule for the Toffoli step of the 3D multiplier circuit. Red bars indicates the application of a SWAP gate between two qubits. The initial mapping of the qubit registers to be multiplied ($A$ and $B$) is indicated with labels of the form $A_i$, $B_i$. The product register is $P$, and $Z$ is an ancilla. In this step of the multiplication, a Toffoli gate is applied to each qubit $P_i$ of the product register, with the corresponding $A_i$ and $B_0$ qubit acting as controls. With respect to the scheduling procedure from Listing \ref{['lst:schedule1']}, there are two rounds: Round 1 represents three repetitions of Line \ref{['line:x']}, one per tile/cube. Round 2 represents Lines \ref{['line:y']}-\ref{['line:last']}. On each row, time flows from left to right. The coloured dotted lines represent the extension of the qubit queues. The gray dotted lines indicate the position of the tile in the left hand side figure where the SWAP gates are performed. The mapping of the qubits illustrated on the left hand side figure is changing during the execution of the schedule (ie. qubits are swapped). For example, in Step 2, after being swapped, $B_0$ is close to the $Z$ ancilla.
• Figure 5: Automatically routed circuits vs. tiled circuits -- SWAP depth and count for different multiplication circuit sizes. The left chart compares SWAP counts and the right chart SWAP Depth. The horizontal axis in both charts represents the size of the multiplication (e.g a 4-bit multiplication), and the vertical axis is the number of SWAP gates and the number of SWAP moments required respectively. The green bars are our tiled multiplier, whereas the red bars are the automatic Google Cirq routing. We conclude that tiling, for these kind of circuits, is more resource efficient.