Thread and Data Mapping in Software Transactional Memory: An Overview
Douglas Pereira Pasqualin, Matthias Diener, André Rauber Du Bois, Maurício Lima Pilla
TL;DR
The paper addresses thread and data mapping for software transactional memory (STM) on NUMA multicore systems. It surveys works that rely solely on information exposed by STM runtimes to guide mapping decisions, highlighting methods like ML-based predictors, sharing-aware mapping, and NUMA-aware data placement. The analysis shows that STM runtime data can enable low-overhead, effective thread mapping, but data mapping remains difficult because STM-visible data represents only a fraction of total memory usage. The authors outline gaps and directions, including online ML, energy efficiency, HTM/hybrid TM integration, and new benchmarks to capture dynamic sharing behavior.
Abstract
In current microarchitectures, due to the complex memory hierarchies and different latencies on memory accesses, thread and data mapping are important issues to improve application performance. Software transactional memory (STM) is an abstraction used for thread synchronization, replacing the use of locks in parallel programming. Regarding thread and data mapping, STM presents new challenges and mapping opportunities, since (1) STM can use different conflict detection and resolution strategies, making the behavior of the application less predictable and; (2) the STM runtime has precise information about shared data and the intensity with each thread accesses them. These unique characteristics provide many opportunities for low-overhead, but precise statistics to guide mapping strategies for STM applications. The main objective of this paper is to survey the existing work about thread and data mapping that uses solely information gathered from the STM runtime to guide thread and data mapping decisions. We also discuss future research directions within this research area.