Scalable almost-linear dynamical Ising machines
Aditya Shukla, Mikhail Erementchouk, Pinaki Mazumder
TL;DR
The paper tackles the scalability bottleneck of continuous-dynamics Ising machines for NP-hard optimization by introducing an almost-linear dissipative Ising model on graphs. It shows that a triangular, piecewise-linear coupling yields a $rank-2$ SDP-relaxation–like framework, with an integrality gap near the Goemans-Williamson bound $\alpha_{GW} \approx 0.877$ and polynomial-time scaling with the number of edges $M$. Software simulations demonstrate good max-cut performance on benchmark graphs and favorable scaling properties, while a CMOS-compatible hardware proof-of-concept validates a practical architecture: vertex spin storage on capacitors, a shared coupler, and adjacency memory. Together, these results indicate a viable path toward large-scale, hardware-based Ising solvers for complex combinatorial optimization tasks, with potential impact on industrially relevant problems requiring efficient approximate solutions.
Abstract
The past decade has seen the emergence of Ising machines targeting hard combinatorial optimization problems by minimizing the Ising Hamiltonian with spins represented by continuous dynamical variables. However, capabilities of these machines at larger scales are yet to be fully explored. We investigate an Ising machine based on a network of almost-linearly coupled analog spins. We show that such networks leverage the computational resource similar to that of the semidefinite positive relaxation of the Ising model. We estimate the expected performance of the almost-linear machine and benchmark it on a set of {0,1}-weighted graphs. We show that the running time of the investigated machine scales polynomially (linearly with the number of edges in the connectivity graph). As an example of the physical realization of the machine, we present a CMOS-compatible implementation comprising an array of vertices efficiently storing the continuous spins on charged capacitors and communicating externally via analog current.
