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Toward A Formalized Approach for Spike Sorting Algorithms and Hardware Evaluation

Tim Zhang, Corey Lammie, Mostafa Rahimi Azghadi, Amirali Amirsoleimani, Majid Ahmadi, Roman Genov

TL;DR

This work tackles the lack of standardized evaluation criteria for spike sorting algorithms and their hardware implementations. It proposes a formalized criteria framework and introduces the Synthetic Simulations Of Extracellular Recordings (SSOER) dataset to enable fair cross-platform benchmarking, including a case study on a simulated RRAM IMC system utilizing Discrete Wavelet Transform for feature extraction. The study demonstrates how alignment, noise robustness, and ground-truth-supported metrics influence performance, with quantified relationships such as a PCC of about 0.7232 between ICV and accuracy. By providing open data and a clear evaluation protocol, the paper facilitates direct comparisons across software and hardware approaches, aiding design decisions for scalable spike-sorting systems in CMOS/IMC contexts.

Abstract

Spike sorting algorithms are used to separate extracellular recordings of neuronal populations into single-unit spike activities. The development of customized hardware implementing spike sorting algorithms is burgeoning. However, there is a lack of a systematic approach and a set of standardized evaluation criteria to facilitate direct comparison of both software and hardware implementations. In this paper, we formalize a set of standardized criteria and a publicly available synthetic dataset entitled Synthetic Simulations Of Extracellular Recordings (SSOER), which was constructed by aggregating existing synthetic datasets with varying Signal-To-Noise Ratios (SNRs). Furthermore, we present a benchmark for future comparison, and use our criteria to evaluate a simulated Resistive Random-Access Memory (RRAM) In-Memory Computing (IMC) system using the Discrete Wavelet Transform (DWT) for feature extraction. Our system consumes approximately (per channel) 10.72mW and occupies an area of 0.66mm$^2$ in a 22nm FDSOI Complementary Metal-Oxide-Semiconductor (CMOS) process.

Toward A Formalized Approach for Spike Sorting Algorithms and Hardware Evaluation

TL;DR

This work tackles the lack of standardized evaluation criteria for spike sorting algorithms and their hardware implementations. It proposes a formalized criteria framework and introduces the Synthetic Simulations Of Extracellular Recordings (SSOER) dataset to enable fair cross-platform benchmarking, including a case study on a simulated RRAM IMC system utilizing Discrete Wavelet Transform for feature extraction. The study demonstrates how alignment, noise robustness, and ground-truth-supported metrics influence performance, with quantified relationships such as a PCC of about 0.7232 between ICV and accuracy. By providing open data and a clear evaluation protocol, the paper facilitates direct comparisons across software and hardware approaches, aiding design decisions for scalable spike-sorting systems in CMOS/IMC contexts.

Abstract

Spike sorting algorithms are used to separate extracellular recordings of neuronal populations into single-unit spike activities. The development of customized hardware implementing spike sorting algorithms is burgeoning. However, there is a lack of a systematic approach and a set of standardized evaluation criteria to facilitate direct comparison of both software and hardware implementations. In this paper, we formalize a set of standardized criteria and a publicly available synthetic dataset entitled Synthetic Simulations Of Extracellular Recordings (SSOER), which was constructed by aggregating existing synthetic datasets with varying Signal-To-Noise Ratios (SNRs). Furthermore, we present a benchmark for future comparison, and use our criteria to evaluate a simulated Resistive Random-Access Memory (RRAM) In-Memory Computing (IMC) system using the Discrete Wavelet Transform (DWT) for feature extraction. Our system consumes approximately (per channel) 10.72mW and occupies an area of 0.66mm in a 22nm FDSOI Complementary Metal-Oxide-Semiconductor (CMOS) process.
Paper Structure (13 sections, 1 equation, 3 figures, 3 tables)

This paper contains 13 sections, 1 equation, 3 figures, 3 tables.

Table of Contents

  1. Introduction
  2. Related Work
  3. Preliminaries
  4. Proposed Set of Formulated Criteria
  5. Accuracy Performance
  6. AUROC
  7. Feature Extraction and Classification Accuracy
  8. Noise Tolerance
  9. Alignment Requirements
  10. Power, Energy, Area, and Latency
  11. The SSOER Dataset
  12. Case Study: A RRAM IMC System
  13. Conclusion

Figures (3)

  • Figure 1: Number of publications related to spike sorting over the decades since its pioneering in the 1950s.
  • Figure 2: A general processing pipeline for spike sorting.
  • Figure 3: (a) The impact of spike alignment techniques on classification accuracy for both algorithms. It can be seen that alignment slightly improves the wavelet but hinders the integer filter technique. (b-c) A comparison of the ICV and accuracy metrics when both algorithms are used for different SNR. Between ICV and accuracy metrics, a PCC of 0.7232 is reported, which indicates weak correlation.