Process, Bias and Temperature Scalable CMOS Analog Computing Circuits for Machine Learning

TL;DR

This work generalizes the previously reported margin-propagation- based analog computing framework for designing novel shape-based analog computing (S-AC) circuits that can be easily cross-mapped across different process nodes that can also be scaled for precision, speed, and power.

Abstract

Analog computing is attractive compared to digital computing due to its potential for achieving higher computational density and higher energy efficiency. However, unlike digital circuits, conventional analog computing circuits cannot be easily mapped across different process nodes due to differences in transistor biasing regimes, temperature variations and limited dynamic range. In this work, we generalize the previously reported margin-propagation-based analog computing framework for designing novel \textit{shape-based analog computing} (S-AC) circuits that can be easily cross-mapped across different process nodes. Similar to digital designs S-AC designs can also be scaled for precision, speed, and power. As a proof-of-concept, we show several examples of S-AC circuits implementing mathematical functions that are commonly used in machine learning (ML) architectures. Using circuit simulations we demonstrate that the circuit input/output characteristics remain robust when mapped from a planar CMOS 180nm process to a FinFET 7nm process. Also, using benchmark datasets we demonstrate that the classification accuracy of a S-AC based neural network remains robust when mapped across the two processes and to changes in temperature.

Figures (15)

• Figure 1: Plot of transconductance efficiency ($g_m/I_d$) as a function of $V_{gs}-V_{th}$ at different process nodes ptm22. The plot also shows the product of $g_m/I_d$ and speed ($f_T$), denoting the efficiency peak obtained in moderate inversion. Plots are shown for n-type planar CMOS and FinFET at different process nodes. Here the maximum supply voltages of each process node can be noted as $1.8V$, $0.8V$ and $0.7V$ for 180nm, 22nm and 7nm, respectively.
• Figure 2: \ref{['exp']} Plot showing the approximation of a non-linear function $\theta(x) \simeq {e^x}$ using linear splines ($S$). Here, the approximations are shown for different spline ($S$) counts i.e, $S = 1,3$, where $Q_1,Q_2,Q_3$ are the tangential points and $T_1,T_2,T_3$ are the tuning points; \ref{['n_sac_ckt']} Implementation of N-type S-AC circuit for $N$ inputs and $S$ splines, the inset shows the circuit implementation of a single S-AC unit using n-type FET and a diode; \ref{['p_sac_ckt']} Implementation of P-type S-AC circuit for $N$ inputs and $S$ splines, the inset shows the circuit implementation of a single S-AC unit using p-type FET and a diode. The circle on the P-type S-AC unit is used to differentiate between an N-type S-AC unit and a P-type S-AC unit.
• Figure 3: Basic S-AC functions implemented by the N-type S-AC circuit and P-type S-AC circuit in different process technology nodes when a single input $x$ is varied: \ref{['protoS1']} for spline-count $S = 1$;\ref{['protoS4']} for spline-count $S = 3$; \ref{['protoS4_allregion_180nmvar']} for different operating regimes in a 180nm process node; \ref{['protoS4_allregion_7nmvar']} for different operating regimes in a 7nm process node. The output current $h(x)$ shown in the plots have been normalized with respect to $I_{max}$, where $I_{max}$ is the maximum current for each biasing regime.
• Figure 4: Basic S-AC functions implemented by the S-AC circuit in a 180nm process node when a single input $x$ is varied: \ref{['temp_var']} when the temperature is varied from $- {45^ \circ }C$ to ${125^ \circ }C$ in 180nm; \ref{['monte_var']} in the presence of device mismatch (upto 5% mismatch) - the plot shown here is for N-type S-AC circuit; \ref{['power_var']} in the presence of power supply voltage variation from ${0.9 }V$ to ${1.8 }V$. The output current $h(x)$ shown in the plots have been normalized with respect to $I_{max}$, where $I_{max}$ is the maximum current for each of the biasing regime.
• Figure 5: Results for S-AC circuit when operating in deep-threshold regime in a 180nm process: \ref{['sourceShifted_char']} MOSFET I-V characteristics showing the effect of source shifting to lower the operating current into the diode leakage regime; \ref{['sourceShifted_sac_ckt']} MOSFET implementation of the N-type S-AC circuit capable of operating in deep-threshold regime; \ref{['sourceShiftedproto']} Normalized output current response of the source-shifted S-AC circuit for $S=1,3$.