An Efficient Architecture and High-Throughput Implementation of CCSDS-123.0-B-2 Hybrid Entropy Coder Targeting Space-Grade SRAM FPGA Technology

TL;DR

The paper addresses the data-rate challenge of hyperspectral on-board processing by delivering an efficient CCSDS-123.0-B-2 Hybrid Entropy Coder architecture implemented as a portable VHDL RTL IP core. Leveraging a systolic, latency-insensitive pipeline and a novel Low Entropy Code-Table lookup design, the implementation achieves a constant 1 sample/cycle throughput, reaching 305 MSamples/s on a space-grade XCKU040 FPGA with a small resource footprint. The design is validated with RTL and FPGA-in-the-loop testing and demonstrated over SpaceFibre interfaces, indicating readiness for space deployments in KCU105/Kintex UltraScale family targets, including XQRKU060. To the best of the authors’ knowledge, this is the first fully compliant, high-throughput CCSDS-123.0-B-2 Hybrid Entropy Coder architecture targeting space-grade FPGA technology, offering significant improvements over prior FLEX- and SHyLoC-based solutions in throughput and scalability.

Abstract

Nowadays, hyperspectral imaging is recognized as cornerstone remote sensing technology. The explosive growth in image data volume and instrument data rates, compete with limited on-board storage resources and downlink bandwidth, making hyperspectral image data compression a mission critical on-board processing task. The Consultative Committee for Space Data Systems (CCSDS) extended the previous issue of the CCSDS-123.0 Recommended Standard for multi- and hyperspectral image compression to provide with Near-Lossless compression functionality. A key feature of the CCSDS-123.0-B-2 is the improved Hybrid Entropy Coder, which at low bit rates, provides substantially better compression performance than the Issue 1 entropy coders. In this paper, we introduce a high-throughput hardware implementation of the CCSDS-123.0-B-2 Hybrid Entropy Coder. The introduced architecture exploits the systolic design pattern to provide modularity and latency insensitivity in a deep and elastic pipeline achieving a constant throughput of 1 sample/cycle with a small FPGA resource footprint. This architecture is described in portable VHDL RTL and is implemented, validated and demonstrated on a commercially available Xilinx KCU105 development board hosting a Xilinx Kintex Ultrascale XCKU040 SRAM FPGA, and thus, is directly transferable to Xilinx Radiation Tolerant Kintex UltraScale XQRKU060 space-grade devices for space deployments. Moreover, state-of-the-art SpaceFibre (ECSS-E-ST-50-11C) serial link interface and test equipment were used in the validation platform to emulate an on-board deployment. The introduced CCSDS-123.0-B-2 Hybrid Entropy Encoder achieves a constant throughput performance of 305 MSamples/s. To the best of our knowledge, this is the first published fully-compliant architecture and high-throughput implementation of the CCSDS-123.0-B-2 Hybrid Entropy Coder, targeting space-grade FPGA technology.

Figures (7)

• Figure 1: Block diagram of the CCSDS-123.0-B-2 compressor ccsds123_b2_blue_book
• Figure 2: Top-level architecture for the proposed Hybrid Entropy Coder
• Figure 3: Code Adaptive Selection Statistics Unit top level architecture
• Figure 4: High Entropy Coder Unit schematic
• Figure 5: Low Entropy Coder Unit top level block diagram