CoFHEE: A Co-processor for Fully Homomorphic Encryption Execution (Extended Version)

TL;DR

CoFHEE presents the first silicon-validated ASIC co-processor dedicated to accelerating low-level polynomial operations for Fully Homomorphic Encryption, implemented in GF 55 nm with a 12 mm^2 die and native support up to $n = 2^{14}$ and 128-bit coefficients. The device emphasizes a memory-centric architecture with a single Processing Element and dual-/single-port SRAMs to realize on-chip NTT-based ciphertext multiplication at 250 MHz, achieving substantial energy efficiency relative to software while enabling on-chip end-to-end FHE primitives for selected workloads. Through detailed design, synthesis, and post-silicon validation, the work demonstrates practical gains in power, latency, and area, and provides open-source RTL for community use. The results indicate that CoFHEE offers meaningful speedups and energy efficiency for specific FHE workloads and lays groundwork for scalable future accelerators with more PEs and memory.

Abstract

The migration of computation to the cloud has raised concerns regarding the security and privacy of sensitive data, as their need to be decrypted before processing, renders them susceptible to potential breaches. Fully Homomorphic Encryption (FHE) serves as a countermeasure to this issue by enabling computation to be executed directly on encrypted data. Nevertheless, the execution of FHE is orders of magnitude slower compared to unencrypted computation, thereby impeding its practicality and adoption. Therefore, enhancing the performance of FHE is crucial for its implementation in real-world scenarios. In this study, we elaborate on our endeavors to design, implement, fabricate, and post-silicon validate CoFHEE, a co-processor for low-level polynomial operations targeting Fully Homomorphic Encryption execution. With a compact design area of $12mm^2$, CoFHEE features ASIC implementations of fundamental polynomial operations, including polynomial addition and subtraction, Hadamard product, and Number Theoretic Transform, which underlie most higher-level FHE primitives. CoFHEE is capable of natively supporting polynomial degrees of up to $n = 2^{14}$ with a coefficient size of 128 bits, and has been fabricated and silicon-verified using 55nm CMOS technology. To evaluate it, we conduct performance and power experiments on our chip, and compare it to state-of-the-art software implementations and other ASIC designs.

Figures (10)

• Figure 1: CoFHEE Top Level Architecture
• Figure 2: Execution flow of operations
• Figure 3: Backend Results
• Figure 4: Proposed ADPLL design and additional Backend Results
• Figure 5: CoFHEE's validation and experimental setup