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Chiplet Actuary: A Quantitative Cost Model and Multi-Chiplet Architecture Exploration

Yinxiao Feng, Kaisheng Ma

TL;DR

A quantitative cost model is built and an analytical method is put forward based on three typical multi-chip integration technologies to analyze the cost benefits from yield improvement, chiplet and package reuse, and heterogeneity to re-examine the actual cost of multi-chip systems from various perspectives.

Abstract

Multi-chip integration is widely recognized as the extension of Moore's Law. Cost-saving is a frequently mentioned advantage, but previous works rarely present quantitative demonstrations on the cost superiority of multi-chip integration over monolithic SoC. In this paper, we build a quantitative cost model and put forward an analytical method for multi-chip systems based on three typical multi-chip integration technologies to analyze the cost benefits from yield improvement, chiplet and package reuse, and heterogeneity. We re-examine the actual cost of multi-chip systems from various perspectives and show how to reduce the total cost of the VLSI system through appropriate multi-chiplet architecture.

Chiplet Actuary: A Quantitative Cost Model and Multi-Chiplet Architecture Exploration

TL;DR

A quantitative cost model is built and an analytical method is put forward based on three typical multi-chip integration technologies to analyze the cost benefits from yield improvement, chiplet and package reuse, and heterogeneity to re-examine the actual cost of multi-chip systems from various perspectives.

Abstract

Multi-chip integration is widely recognized as the extension of Moore's Law. Cost-saving is a frequently mentioned advantage, but previous works rarely present quantitative demonstrations on the cost superiority of multi-chip integration over monolithic SoC. In this paper, we build a quantitative cost model and put forward an analytical method for multi-chip systems based on three typical multi-chip integration technologies to analyze the cost benefits from yield improvement, chiplet and package reuse, and heterogeneity. We re-examine the actual cost of multi-chip systems from various perspectives and show how to reduce the total cost of the VLSI system through appropriate multi-chiplet architecture.
Paper Structure (18 sections, 8 equations, 10 figures)

This paper contains 18 sections, 8 equations, 10 figures.

Table of Contents

  1. Introduction
  2. Background
  3. Multi-chip Integration
  4. Yield Model
  5. NRE and RE Cost
  6. Chiplet Actuary Model
  7. High Level Abstraction
  8. RE Cost Model
  9. NRE Cost Model
  10. Model Validation and Discussion
  11. Validation and Comparison of RE cost
  12. Total Cost Comparison of Single System
  13. Chiplet Reuse Scheme Exploration
  14. Single Chiplet Multiple Systems (SCMS)
  15. One Center Multiple Extensions (OCME)
  16. ...and 3 more sections

Figures (10)

  • Figure 1: Different multi-chip integration technologies Synopsys
  • Figure 2: Yield/Cost-Area relation of different technologies
  • Figure 3: High-level cost model diagram
  • Figure 4: Normalized RE cost comparison among different integrations under different technologies
  • Figure 5: Normalized RE cost comparison for AMD's chiplet architecture.
  • ...and 5 more figures