Computing unsatisfiable cores for LTLf specifications
Marco Roveri, Claudio Di Ciccio, Chiara Di Francescomarino, Chiara Ghidini
TL;DR
This work addresses extracting unsatisfiable cores from LTLf specifications by proposing four UC extraction algorithms that adapt leading LTL/LTLf satisfiability methods. It develops two complementary pathways: LTLet-based reductions (BDDs, SAT, temporal resolution) and native LTLf SAT approaches, augmented with activation variables and past-to-future transformations to handle past operators. The paper introduces preliminary results enabling past-operator handling (via extended $f2l()$ and $P2F$) and activation-variable conditioning, then demonstrates UC extraction through BDD-based, SAT-based, TR-based, and native SAT methods, with an extensive experimental evaluation showing complementary strengths among tools. The findings enable practical debugging of inconsistent LTLf specifications and provide a toolkit of approaches that practitioners can combine to locate causes of unsatisfiability in domains like BPM, planning, and run-time monitoring.
Abstract
Linear-time temporal logic on finite traces (LTLf) is rapidly becoming a de-facto standard to produce specifications in many application domains (e.g., planning, business process management, run-time monitoring, reactive synthesis). Several studies approached the respective satisfiability problem. In this paper, we investigate the problem of extracting the unsatisfiable core in LTLf specifications. We provide four algorithms for extracting an unsatisfiable core leveraging the adaptation of state-of-the-art approaches to LTLf satisfiability checking. We implement the different approaches within the respective tools and carry out an experimental evaluation on a set of reference benchmarks, restricting to the unsatisfiable ones. The results show the feasibility, effectiveness, and complementarities of the different algorithms and tools.
