Physical based compact model of Y-Flash memristor for neuromorphic computation

TL;DR

A physical-based compact model is provided that describes Y-Flash memristor performance both in DC and AC regimes, and consistently describes the dynamic program and erase operations.

Abstract

Y-Flash memristors utilize the mature technology of single polysilicon floating gate non-volatile memories (NVM). It can be operated in a two-terminal configuration similar to the other emerging memristive devices, i.e., resistive random-access memory (RRAM), phase-change memory (PCM), etc. Fabricated in production complementary metal-oxide-semiconductor (CMOS) technology, Y-Flash memristors allow excellent repro-ducibility reflected in high neuromorphic products yields. Working in the subthreshold region, the device can be programmed to a large number of fine-tuned intermediate states in an analog fashion and allows low readout currents (1 nA ~ 5 $μ$ A). However, currently, there are no accurate models to describe the dynamic switching in this type of memristive device and account for multiple operational configurations. In this paper, we provide a physical-based compact model that describes Y-Flash memristor performance both in DC and AC regimes, and consistently describes the dynamic program and erase operations. The model is integrated into the commercial circuit design tools and is ready to be used in applications related to neuromorphic computation.

Figures (5)

• Figure 1: (a) Schematic of the Y-Flash structure; (b) equivalent circuit accounting for parasitic capacitors, transistors, and p-n diodes; (c) the symbol of the Y-Flash device with external terminals; (d) Y-Flash array for VMM; (e) programming of the devices in an array; (f) erasing of the devices in an array.
• Figure 2: Comparison of the measured and modeled DC I-V characteristics Y-Flash device in read mode for a pristine (non-programmed) device ($Q_{FG}=0$): (a) in logarithmic scale; (b) in linear scale (inset: schematic of the read operation). Pulse reading of the model implemented in circuit simulator: (c) pulse width 5 ns, rise time 1 ns; (d) pulse width 50 ns, rise time 10 ns.
• Figure 3: (a) Schematic of the program operation; (b) mechanism of hot carrier injection into the FG in program operation; (c) readout I-V characteristics for subsequent programming pulses; (d) readout current at 2V as a function of accumulated program time; (e) FG charge as a function of the accumulated program time; (f) schematic of the erase operation; (g) mechanisms of FG discharge in the erase operation; (h) readout of the device for subsequent erase pulses; (i) readout current at 2V as the function of accumulated erase time; (j) FG charge as a function of the accumulated erase time.
• Figure 4: Cycling of the program and erase operations showing excellent cycle-to-cycle uniformity.
• Figure 5: Device-to-device variations and modeling. Device-to-device variations for (a) the pulsed program operations ($V_P=5V$, pulse width 200 $\mu$s), and (b) the pulsed erase operations ($V_E=8V$, pulse width 100 $\mu$s); Statistical total (c) program time and (d) erase time from the experiments and model results.