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A 120dB Programmable-Range On-Chip Pulse Generator for Characterizing Ferroelectric Devices

Shyam Narayanan, Erika Covi, Viktor Havel, Charlotte Frenkel, Suzanne Lancaster, Quang Duong, Stefan Slesazeck, Thomas Mikolajick, Melika Payvand, Giacomo Indiveri

TL;DR

This paper tackles the challenge of characterizing ferroelectric devices by requiring precise, wide‑range voltage pulses directly on chip. It introduces a 120 dB programmable on‑chip pulse generator implemented in a 180 nm CMOS process, delivering pulses from $10~\mathrm{ns}$ to $10~\mathrm{ms}$ with $\pm 2.5\%$ width accuracy, thereby bypassing external RC bottlenecks. The design combines an edge detector, a 7‑bit IDAC, an 8‑bit CDAC, and a hysteretic comparator to control ramp‑based pulse generation via $I_{DAC}$ and $C_{DAC}$, with the key relation $I_{DAC} = C_{DAC} \cdot \frac{\Delta V_{REF}}{\Delta t}$. Fabricated devices demonstrate wide programmability, BEOL integration with ferroelectric devices, and calibration‑driven pulse fidelity, enabling accurate switching‑kinetics studies crucial for FeCAP, FeFET, and FTJ devices in neuromorphic applications.

Abstract

Novel non-volatile memory devices based on ferroelectric thin films represent a promising emerging technology that is ideally suited for neuromorphic applications. The physical switching mechanism in such films is the nucleation and growth of ferroelectric domains. Since this has a strong dependence on both pulse width and voltage amplitude, it is important to use precise pulsing schemes for a thorough characterization of their behaviour. In this work, we present an on-chip 120 dB programmable range pulse generator, that can generate pulse widths ranging from 10ns to 10ms $\pm$2.5% which eliminates the RLC bottleneck in the device characterisation setup. We describe the pulse generator design and show how the pulse width can be tuned with high accuracy, using Digital to Analog converters. Finally, we present experimental results measured from the circuit, fabricated using a standard 180nm CMOS technology.

A 120dB Programmable-Range On-Chip Pulse Generator for Characterizing Ferroelectric Devices

TL;DR

This paper tackles the challenge of characterizing ferroelectric devices by requiring precise, wide‑range voltage pulses directly on chip. It introduces a 120 dB programmable on‑chip pulse generator implemented in a 180 nm CMOS process, delivering pulses from to with width accuracy, thereby bypassing external RC bottlenecks. The design combines an edge detector, a 7‑bit IDAC, an 8‑bit CDAC, and a hysteretic comparator to control ramp‑based pulse generation via and , with the key relation . Fabricated devices demonstrate wide programmability, BEOL integration with ferroelectric devices, and calibration‑driven pulse fidelity, enabling accurate switching‑kinetics studies crucial for FeCAP, FeFET, and FTJ devices in neuromorphic applications.

Abstract

Novel non-volatile memory devices based on ferroelectric thin films represent a promising emerging technology that is ideally suited for neuromorphic applications. The physical switching mechanism in such films is the nucleation and growth of ferroelectric domains. Since this has a strong dependence on both pulse width and voltage amplitude, it is important to use precise pulsing schemes for a thorough characterization of their behaviour. In this work, we present an on-chip 120 dB programmable range pulse generator, that can generate pulse widths ranging from 10ns to 10ms 2.5% which eliminates the RLC bottleneck in the device characterisation setup. We describe the pulse generator design and show how the pulse width can be tuned with high accuracy, using Digital to Analog converters. Finally, we present experimental results measured from the circuit, fabricated using a standard 180nm CMOS technology.
Paper Structure (9 sections, 2 equations, 9 figures, 2 tables)

This paper contains 9 sections, 2 equations, 9 figures, 2 tables.

Table of Contents

  1. Introduction
  2. System Architecture
  3. Edge detector
  4. Wide-Range IDAC
  5. $C_{DAC}$
  6. Hysteretic Comparator
  7. Implementation and system level simulation
  8. Hardware setup and electrical characterization
  9. Conclusion

Figures (9)

  • Figure 1: Switching transitions: (\ref{['fig:switching_on']}) switched polarization as a function of pulse width for different pulse amplitudes, for a bilayer FTJ device. (\ref{['fig:switching_fitting']}) Time needed to switch 50% of polarization for each voltage amplitude, expected switching curve for HZO only (black dotted line from materano2020polarization) and asymptotic RC-cutoff (red dotted line)
  • Figure 2: Architecture of the Pulse Generator
  • Figure 3: MonteCarlo Analysis of $I_{DAC}$ Error
  • Figure 4: Differential to single- ended hysteretic comparator
  • Figure 5: Pulse generator layout
  • ...and 4 more figures