Modeling Short-Range Microwave Networks to Scale Superconducting Quantum Computation

TL;DR

This paper investigates scaling superconducting quantum computers with chiplet architectures interconnected by short-range microwave links. It develops a physics-to-network modeling framework that connects inter-chiplet channels and local SWAPs to network-level performance, and analyzes multiple topologies to assess trade-offs between connectivity, latency, and noise. Key contributions include realistic quantum-channel models (Choi-based), a simple yet extrapolatable fidelity decay model, an error-detection scheme for links, and comparative results showing chiplets can reduce data-movement error compared to monolithic designs under plausible link fidelities. The work highlights the potential of short-range quantum intranets to accelerate progress toward fault-tolerant, large-scale quantum computation, and provides a co-design blueprint and open-source resources for the quantum computing community.

Abstract

A core challenge for superconducting quantum computers is to scale up the number of qubits in each processor without increasing noise or cross-talk. Distributed quantum computing across small qubit arrays, known as chiplets, can address these challenges in a scalable manner. We propose a chiplet architecture over microwave links with potential to exceed monolithic performance on near-term hardware. Our methods of modeling and evaluating the chiplet architecture bridge the physical and network layers in these processors. We find evidence that distributing computation across chiplets may reduce the overall error rates associated with moving data across the device, despite higher error figures for transfers across links. Preliminary analyses suggest that latency is not substantially impacted, and that at least some applications and architectures may avoid bottlenecks around chiplet boundaries. In the long-term, short-range networks may underlie quantum computers just as local area networks underlie classical datacenters and supercomputers today.

Figures (11)

• Figure 1: CX implementation of SWAP operation between two qubits.
• Figure 2: The black lines connecting physical qubits indicate on-chip connections while the red lines indicate inter-chip microwave links. (a) Heavy-hex, where red lines illustrate possible link placements in 38-q chiplet. (b) Four 27-q chiplets with links on nodes of local coordination number 1. (c) Monolithic grid. (d) Tree of $3 \times 3$ grids. (e) Random graph with degree 3 and good spectral gap. Here each node (shown in blue) would be replaced by connections to a chiplet. (f) Octagonal chips are connected via links. (g) Octagonal chips are stacked with heavy-hex in vertically alternating layers. (h) Octagonal chips are stacked with squares in vertically alternating layers.
• Figure 3: Comparison of QC topology graph diameter vs. number of qubits for proposed architectures. Graph diameter quantifies the maximum number of swap operations needed for a qubit to transit from one end to another.
• Figure 4: Comparison of QC topology spectral gap vs. number of qubits for proposed architectures. The spectral gap as in Definition \ref{['def:specgap']} quantifies the rate at which random walks on the graph converge toward a uniform distribution on nodes. Graphs with few bottlenecks tend to have higher spectral gaps.
• Figure 5: Path of SWAP gate chains through IBM Falcon processors.

Theorems & Definitions (2)

• Definition 4.1
• Definition 4.2