Simultaneous execution of quantum circuits on current and near-future NISQ systems

TL;DR

The paper tackles the challenge of running multiple quantum circuits concurrently on NISQ devices in the presence of crosstalk. It introduces palloq, a two-part system with a knapsack-like circuit composer and a crosstalk-aware layout, plus a low-cost detection protocol based on SimRB to quantify hardware suitability for multi-programming. Experiments on IBM Quantum Experience show a clear trade-off between output fidelity and throughput, with a physical qubit buffer improving reliability at the expense of speed, captured by a definition such as $PST = \frac{N_{success}}{N_{total}}$. The results support a practical workflow for cloud QC that reduces crosstalk characterization costs and enhances scalable, high-throughput operation across current and near-future NISQ systems.

Abstract

In the NISQ era, multi-programming of quantum circuits (QC) helps to improve the throughput of quantum computation. Although the crosstalk, which is a major source of noise on NISQ processors, may cause performance degradation of concurrent execution of multiple QCs, its characterization cost grows quadratically in processor size. To address these challenges, we introduce palloq (parallel allocation of QCs) for improving the performance of quantum multi-programming on NISQ processors while paying attention to the combination of QCs in parallel execution and their layout on the quantum processor, and reducing unwanted interference between QCs caused by crosstalk. We also propose a software-based crosstalk detection protocol that efficiently and successfully characterizes the hardware's suitability for multi-programming. We found a trade-off between the success rate and execution time of the multi-programming. This would be attractive not only to quantum computer service but also to users around the world who want to run algorithms of suitable scale on NISQ processors that have recently attracted great attention and are being enthusiastically investigated.

Figures (10)

• Figure 1: Cloud Quantum Computing Architecture Various implementations of quantum processors have been proposed jones2001quantumclarke2008superconductingkielpinski2002architecturedutt2007quantumo2009photonic. As the core of the service, the quantum processor provides its computing resources by performing quantum operations and measurements. Digital Analog control exchanges the quantum and classical information by converting program instruction into analog signals and measurement results into classical data. The real-time control system is responsible for classical-quantum interaction, mid-circuit measurements, and feed-forward operations. Another end of the cloud computing is the browser-based user interface. End-users create the requests (jobs) on a web browser, send them to the system via a web server through the Internet, and receive the results of the computation. The browser-based user interface provides AAA (authentication, authorization, accountability), and in some cases, quantum programming tool and its development environment, such as a GUI-based quantum circuit composer.
• Figure 2: The idea of multiple execution. The lattice graph represents the quantum processor, nodes denote qubits and edges are two qubits connection. The QC with the green box represents quantum circuits placed on physical qubits of the processor. \ref{['single_execution']} represents single quantum circuit execution. Because the limited sized circuits are tolerable on NISQ system, the idle qubits (yellow circles) reduce the throughput of the processor. \ref{['multiple_execution']} describes the idea of multiple circuit execution concurrently. This approach reduces idle qubits and is expected to increase the throughput.
• Figure 3: Simultaneous Randomized Benchmarking (SimRB) Upper diagram shows ordinary RB on two-qubits. RB applies random clifford operations with varying the length of gates and estimates its error rates. In the case of Simultaneous RB, applying RB on more than two hardware areas and comparing the error rates to single RB case, measure the conditional error rates of hardware qubits. In this research, we only conducted two-qubits RB and SimRB.
• Figure 4: Toffoli gate on chain topology
• Figure 5: Multiple Toffoli placement varying physical buffer. The graph denotes the quantum processor, nodes are qubits and edges are two qubit connection of the superconducting qubit system. The blue boxes represent the quantum circuits of Toffoli operation placed on physical qubits. We placed 5 circuits and vary the physical buffer, then measure the success rate of the Toffoli placed in the center.