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Cascode Cross-Coupled Stage High-Speed Dynamic Comparator in 65 nm CMOS

Komala Krishna, Nandakumar Nambath

TL;DR

The work tackles the challenge of achieving high-speed, high-resolution ADCs with dynamic comparators by addressing poor performance at small input differences $ΔV_{IN}$ in conventional double-tail designs. It introduces a cascode cross-coupled dynamic comparator that increases pre-amplifier differential gain and reduces the preamplifier common-mode $V_{CM}$, leading to faster latch regeneration and improved sensitivity to small inputs. In 65 nm CMOS with $V_{DD}=1.1$ V, the approach achieves fast delays (e.g., $t obreak ilde{} obreak ext{≈}46.5$ ps at $ΔV_{IN}=1$ mV, with $V_{CM}$ and other conditions) and substantial improvements over conventional DT and some state-of-the-art designs, while maintaining acceptable offset and energy characteristics. Overall, the proposed topology offers a practical path to high-speed, high-resolution ADCs by enhancing pre-amplifier gain and stabilizing common-mode behavior across the input range, validated through detailed simulations and layout considerations in 65 nm CMOS.

Abstract

Dynamic comparators are the core of high-speed, high-resolution analog-to-digital converters (ADCs) used for communication applications. Most of the dynamic comparators attain high-speed operation only for sufficiently high input difference voltages. The comparator performance degrades at small input difference voltages due to a limited pre-amplifier gain, which is undesirable for high-speed, high-resolution ADCs. To overcome this drawback, a cascode cross-coupled dynamic comparator is presented. The proposed comparator improves the differential gain of the pre-amplifier and reduces the common-mode voltage seen by the latch, which leads to a much faster regeneration at small input difference voltages. The proposed comparator is designed, simulated, and compared with the state-of-the-art techniques in 65 nm CMOS technology. The results demonstrate that the proposed comparator achieves a delay of 46.5 ps at 1 mV input difference, and a supply of 1.1 V.

Cascode Cross-Coupled Stage High-Speed Dynamic Comparator in 65 nm CMOS

TL;DR

The work tackles the challenge of achieving high-speed, high-resolution ADCs with dynamic comparators by addressing poor performance at small input differences in conventional double-tail designs. It introduces a cascode cross-coupled dynamic comparator that increases pre-amplifier differential gain and reduces the preamplifier common-mode , leading to faster latch regeneration and improved sensitivity to small inputs. In 65 nm CMOS with V, the approach achieves fast delays (e.g., ps at mV, with and other conditions) and substantial improvements over conventional DT and some state-of-the-art designs, while maintaining acceptable offset and energy characteristics. Overall, the proposed topology offers a practical path to high-speed, high-resolution ADCs by enhancing pre-amplifier gain and stabilizing common-mode behavior across the input range, validated through detailed simulations and layout considerations in 65 nm CMOS.

Abstract

Dynamic comparators are the core of high-speed, high-resolution analog-to-digital converters (ADCs) used for communication applications. Most of the dynamic comparators attain high-speed operation only for sufficiently high input difference voltages. The comparator performance degrades at small input difference voltages due to a limited pre-amplifier gain, which is undesirable for high-speed, high-resolution ADCs. To overcome this drawback, a cascode cross-coupled dynamic comparator is presented. The proposed comparator improves the differential gain of the pre-amplifier and reduces the common-mode voltage seen by the latch, which leads to a much faster regeneration at small input difference voltages. The proposed comparator is designed, simulated, and compared with the state-of-the-art techniques in 65 nm CMOS technology. The results demonstrate that the proposed comparator achieves a delay of 46.5 ps at 1 mV input difference, and a supply of 1.1 V.
Paper Structure (7 sections, 6 equations, 6 figures, 1 table)

This paper contains 7 sections, 6 equations, 6 figures, 1 table.

Table of Contents

  1. Introduction
  2. Conventional Double Tail Dynamic Comparator
  3. Proposed Cascode Cross-Coupled Dynamic Comparator
  4. Operation
  5. Delay Analysis
  6. Results and Discussion
  7. Conclusion

Figures (6)

  • Figure 1: Schematic of the proposed double tail comparator with cascode cross-coupled pair to enhance pre-amplifier gain. The cascode cross-coupled pair made up of $\text{M}_\text{3}$, $\text{M}_\text{4}$, $\text{M}_\text{c1}$, and $\text{M}_\text{c2}$ improves the pre-amplifier performance.
  • Figure 2: Transient analysis results of the proposed comparator in comparison with the conventional one when $\Delta V_{IN}=10$ mV, $\text{V}_\text{CM}=0.77$ V: (a) output nodes and (b) intermediate nodes.
  • Figure 3: Delay variation with $\Delta V_{IN}$ of the proposed comparator. Inset shows the improved delay for small values of $\Delta V_{IN}$.
  • Figure 4: (a) Delay versus $\text{V}_\text{CM}$ at $\Delta V_{IN}$=10 mV (b) Delay versus $\text{V}_\text{DD}$ of the proposed comparator in comparison to that of the state-of-the-art topologies.
  • Figure 5: Layout of the proposed comparator.
  • ...and 1 more figures