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An Algorithm for Reversible Logic Circuit Synthesis Based on Tensor Decomposition

Hochang Lee, Kyung Chul Jeong, Daewan Han, Panjin Kim

TL;DR

This work presents a reversible logic circuit synthesis method based on tensor-size reduction, converting an $n$-bit substitution map $P_n$ toward a product form $P_{n-1}\otimes I_2$ iteratively until the problem reduces to small blocks. It leverages a gate library of $C^mX$ gates (decomposed to $C^0X$, $C^1X$, $C^2X$) and treats Toffoli gates as the primary cost metric to drive optimization. The algorithm combines heuristic mixing, preprocessing, and a generalized size-reduction routine to handle unstructured permutations, achieving promising Toffoli-count performance on cryptographic S-boxes such as AES, DES, Skipjack, and KHADZAD, with in-place circuit designs demonstrated. While the method incurs $O(n2^{2n})$ time complexity, its strength lies in producing compact, garbageless reversible circuits for otherwise intractable, structureless permutation maps, with practical code available for experimentation and extension to tensor-network optimizations. The approach thus offers a scalable baseline for automated reversible synthesis and potential cryptographic applications where non-Clifford gate costs are critical.

Abstract

An algorithm for reversible logic synthesis is proposed. The task is, for a given $n$-bit substitution map $P_n: \{0,1\}^n \rightarrow \{0,1\}^n$, to find a sequence of reversible logic gates that implements the map. The gate library adopted in this work consists of multiple-controlled Toffoli gates denoted by $C^m\!X$, where $m$ is the number of control bits that ranges from 0 to $n-1$. Controlled gates with large $m \,\,(>2)$ are then further decomposed into $C^0\!X$, $C^1\!X$, and $C^2\!X$ gates. A primary concern in designing the algorithm is to reduce the use of $C^2\!X$ gate (also known as Toffoli gate) which is known to be universal. The main idea is to view an $n$-bit substitution map as a rank-$2n$ tensor and to transform it such that the resulting map can be written as a tensor product of a rank-($2n-2$) tensor and the $2\times 2$ identity matrix. Let $\mathcal{P}_n$ be a set of all $n$-bit substitution maps. What we try to find is a size reduction map $\mathcal{A}_{\rm red}: \mathcal{P}_n \rightarrow \{P_n: P_n = P_{n-1} \otimes I_2\}$. %, where $I_m$ is the $m\times m$ identity matrix. One can see that the output $P_{n-1} \otimes I_2$ acts nontrivially on $n-1$ bits only, meaning that the map to be synthesized becomes $P_{n-1}$. The size reduction process is iteratively applied until it reaches tensor product of only $2 \times 2$ matrices.

An Algorithm for Reversible Logic Circuit Synthesis Based on Tensor Decomposition

TL;DR

This work presents a reversible logic circuit synthesis method based on tensor-size reduction, converting an -bit substitution map toward a product form iteratively until the problem reduces to small blocks. It leverages a gate library of gates (decomposed to , , ) and treats Toffoli gates as the primary cost metric to drive optimization. The algorithm combines heuristic mixing, preprocessing, and a generalized size-reduction routine to handle unstructured permutations, achieving promising Toffoli-count performance on cryptographic S-boxes such as AES, DES, Skipjack, and KHADZAD, with in-place circuit designs demonstrated. While the method incurs time complexity, its strength lies in producing compact, garbageless reversible circuits for otherwise intractable, structureless permutation maps, with practical code available for experimentation and extension to tensor-network optimizations. The approach thus offers a scalable baseline for automated reversible synthesis and potential cryptographic applications where non-Clifford gate costs are critical.

Abstract

An algorithm for reversible logic synthesis is proposed. The task is, for a given -bit substitution map , to find a sequence of reversible logic gates that implements the map. The gate library adopted in this work consists of multiple-controlled Toffoli gates denoted by , where is the number of control bits that ranges from 0 to . Controlled gates with large are then further decomposed into , , and gates. A primary concern in designing the algorithm is to reduce the use of gate (also known as Toffoli gate) which is known to be universal. The main idea is to view an -bit substitution map as a rank- tensor and to transform it such that the resulting map can be written as a tensor product of a rank-() tensor and the identity matrix. Let be a set of all -bit substitution maps. What we try to find is a size reduction map . %, where is the identity matrix. One can see that the output acts nontrivially on bits only, meaning that the map to be synthesized becomes . The size reduction process is iteratively applied until it reaches tensor product of only matrices.

Paper Structure

This paper contains 23 sections, 4 theorems, 22 equations, 5 figures, 4 tables, 7 algorithms.

Table of Contents

  1. Introduction
  2. Background
  3. Gate Library
  4. Permutation Circuit Synthesis
  5. Related Works
  6. Basic Idea
  7. Matrix Size Reduction
  8. Definitions and Conventions
  9. Glossary
  10. Size Reduction Algorithm
  11. Complexity
  12. Algorithm
  13. Heuristic Mixing
  14. Preprocessing
  15. Generalized Size Reduction Algorithm
  16. ...and 8 more sections

Key Result

proposition thmcounterproposition

Let $l$ be the number of left-allocated blocks, and $m$ be the smallest positive integer satisfying Eq. (eq:m). Define a function $h_n: \mathbb{N} \rightarrow \mathbb{Z}$, $h_n (x) = 2^{n} - 2^{n - (x-1)}$. There exists at least one relevant row pair $r_\alpha, r_\beta$ such that where $\alpha,\beta$ are column numbers of $r_\alpha, r_\beta$, respectively.

Figures (5)

  • Figure 1: Truth tables and circuit symbols for (a) CNOT and (b) Toffoli gates. (c) Decomposition of $C^4\!X$ into five ($= 2\cdot 4 -3$) Toffoli gates. Here $a,b,c,d$ are input control bits and $w_0, w_1$ are zeroed work bits.
  • Figure 2: (a) Relation between $m$ and $l$. (b) Column positions (rectangle) and block-wise positions (two conjoined rectangles) in a permutation. Constructed blocks are to be allocated to the left, occupying block-wise positions denoted by $i$. When one tries to construct and allocate a new block at $i$-th position, $l$ equals $i$ and thus $m$ is determined as specified. Dashed vertical lines divide the number of column positions to be as ratios 1:1, 3:1, 7:1, and so on.
  • Figure 3: $L_\delta$ and $R_\delta$ for $\delta=1,2,3$.
  • Figure 4: Sampling tests for $n\in\{6,7,8\}$ and $t\in\{0,1,2,3\}$. Each figure shows the percentage of samples as a function of $\lambda - 2^{n-1}$ (or $|\lambda - 2^{n-1}|$), where $\lambda$ is defined in the main text. In other words, figures show how far the permutations are from the ratio $x:y:0.5$ (and especially $\lambda - 2^{n-1} = 0$ means the ratio is exactly $x:y:0.5$). For $t=2$ where two CX gates have been applied, we were already able to find the desired permutations with high probability. The margin of error is $\pm1.55$% at $95$% confidence level.
  • Figure 5: Quality bounds on size reduction of $n$-bit permutations (Eq. (\ref{['eq:reduction-bound']})) joined by dashed lines, and the statistical averages of the output qualities denoted by the red and blue bars for 1000 randomly generated instances for each $n$ with depth-0 (blue) and depth-1 (red) partial search. Min-Max values are also marked with black bars.

Theorems & Definitions (12)

  • definition thmcounterdefinition
  • definition thmcounterdefinition
  • definition thmcounterdefinition
  • definition thmcounterdefinition
  • remark thmcounterremark
  • proposition thmcounterproposition
  • proof
  • lemma thmcounterlemma
  • proof
  • lemma thmcounterlemma
  • ...and 2 more