Pulse-engineered Controlled-V gate and its applications on superconducting quantum device

TL;DR

The paper demonstrates pulse-engineered CV gates implemented via OpenPulse on IBM superconducting devices, achieving a substantial reduction in two-qubit gate time (approximately 65.5% shorter than CX-based CV implementations) and a modest fidelity improvement. Leveraging Cartan decomposition and Weyl chamber geometry, it characterizes the set of two-qubit gates accessible with two or three CV gates, showing that CV gates can realize a broader class of operations with lower time costs. It provides concrete demonstrations for $\sqrt{\text{iSWAP}}$, $\sqrt{\text{SWAP}}$, and a linearly-coupled three-qubit Toffoli gate, reporting faster operation and higher average fidelity when CV gates are used. These results suggest that adding pulse-engineered CV gates to the IBM Quantum gate toolbox can shorten circuit duration and potentially improve precision for various quantum algorithms, with further gains possible by mitigating residual ZZ interactions.

Abstract

In this paper, we demonstrate that, by employing OpenPulse design kit for IBM superconducting quantum devices, the controlled-V gate (CV gate) can be implemented in about half the gate time to the controlled-X (CX or CNOT gate) and consequently 65.5\% reduced gate time compared to the CX-based implementation of CV. Then, based on the theory of Cartan decomposition, we characterize the set of all two-qubit gates implemented with only two or three CV gates; using pulse-engineered CV gates enables us to implement these gates with shorter gate time and possibly better gate fidelity than the CX-based one, as actually demonstrated in two examples. Moreover, we showcase the improvement of linearly-coupled three-qubit Toffoli gate, by implementing it with the pulse-engineered CV gate, both in gate time and the averaged output-state fidelity. These results imply the importance of our CV gate implementation technique, which, as an additional option for the basis gate set design, may shorten the overall computation time and consequently improve the precision of several quantum algorithms executed on a real device.

Figures (9)

• Figure 1: (a) Pulse sequence for CV gate in the QASM implementation. (b) Pulse sequence for CV gate implemented by OpenPulse with the CR pulse duration 101.5 ns.
• Figure 2: (a) Weyl chamber (tetrahedron $OA_1A_2A_3$) contains all the locally equivalent class of two-qubit operations, with the exception of points on its base (see the caption of Fig. \ref{['2D']}). (b) Five important points in the Weyl chamber; at each point typical locally equivalent gates are indicated. (c) Colored area, i.e., the union of tetrahedra $OB_1B_2B_3$ and $A_1C_1C_2C_3$ in the Weyl chamber, shows the set of two-qubit gate realized with three CV gates. All the points in the figures are defined as $B_1 =[3\pi/4,0,0]$, $B_2 =[3\pi/8,3\pi/8,0]$, $B_3 =[\pi/4,\pi/4,\pi/4]$, $C_1 =[\pi/4,0,0]$, $C_2 =[5\pi/8,3\pi/8,0]$, $C_3 =[3\pi/4,\pi/4,\pi/4]$.
• Figure 3: Area of two-qubit gates generated with 2 CX or CV gates. 2 CX gates can generate any gate represented by the point in the triangle area $OA_1A_2$, which is the base of Weyl chamber. The blue region represents the set of gates that 2 CV gates can generate. The triangle areas $OLB$ and $A_1LC$ are locally equivalent; in particular, $B =[\pi/4,\pi/4,0]$ and $C =[3\pi/4,\pi/4,0]$ are equivalent points corresponding to $\sqrt{\hbox{iSWAP}}$ gate. The lines $OL$ and $LA_1$ (overlaid with pink belt) correspond to the set of controlled-$U$ gates.
• Figure 4: Circuit diagram for $\sqrt{iSWAP}_{CX}$ gate (middle) and $\sqrt{iSWAP}_{CV}$ gate (lower).
• Figure 5: Circuit diagram for $\sqrt{SWAP}_{CX}$ gate (middle) and $\sqrt{SWAP}_{CV}$ gate (lower).