Compressed Shaping: Concept and FPGA Demonstration
Tsuyoshi Yoshida, Koji Igarashi, Magnus Karlsson, Erik Agrell
TL;DR
The paper addresses the inefficiency of assuming source uniformity in probabilistic shaping for optical communications by introducing compressed shaping, a fixed-length data-compression plus PS approach implemented with hierarchical distribution matching. It establishes entropy-based bounds, e.g., $H(X_c)=m_s+H(A_c)$ and $H_{LB}=m_s+H(S)kn$, and the rate-loss relationship $R_{\mathrm{loss}}(S,A)=H(A)-H(S)kn$, to quantify gains from exploiting source nonuniformity. Numerical simulations across $8$–$128$-QAM show reduced $E_{2d}$ and lower required SNR under nonuniform sources, while FPGA demonstrations achieve up to $153\,\mathrm{Gb/s}$ for $16$-QAM and $113\,\mathrm{Gb/s}$ for $64$-QAM with manageable hardware overhead; real-time tests confirm no error floor and only modest BER penalties relative to traditional DM schemes. This work provides a practical pathway to joint source–channel coding in fiber optics, enabling power-efficient, high-throughput PS systems via a fixed-length, source-sensitive DM architecture.
Abstract
Probabilistic shaping (PS) has been widely studied and applied to optical fiber communications. The encoder of PS expends the number of bit slots and controls the probability distribution of channel input symbols. Not only studies focused on PS but also most works on optical fiber communications have assumed source uniformity (i.e. equal probability of marks and spaces) so far. On the other hand, the source information is in general nonuniform, unless bit-scrambling or other source coding techniques to balance the bit probability is performed. Interestingly, one can exploit the source nonuniformity to reduce the entropy of the channel input symbols with the PS encoder, which leads to smaller required signal-to-noise ratio at a given input logic rate. This benefit is equivalent to a combination of data compression and PS, and thus we call this technique compressed shaping. In this work, we explain its theoretical background in detail, and verify the concept by both numerical simulation and a field programmable gate array (FPGA) implementation of such a system. In particular, we find that compressed shaping can reduce power consumption in forward error correction decoding by up to 90% in nonuniform source cases. The additional hardware resources required for compressed shaping are not significant compared with forward error correction coding, and an error insertion test is successfully demonstrated with the FPGA.
