Comparison of Cloud-Based Ion Trap and Superconducting Quantum Computer Architectures

TL;DR

This paper benchmarks cloud-based quantum computers based on ion-trap qubits and superconducting qubits to assess connectivity, SPAM, and two-qubit gate performance using simple circuits and a scaling Bernstein-Vazirani (BV) algorithm. The BV experiments leverage a hidden $n$-bit string $\mathbf{a}$ encoded via CNOT patterns and retrieved with a single quantum query, illustrating how topology and crosstalk influence scalability in cloud QCs. Key findings show IonQ's SPAM is substantially lower and its full connectivity reduces SWAP overhead, while superconducting devices exhibit depth-dependent gate noise and higher SPAM with notable variability across platforms; BV results highlight how connectivity and calibration affect scalability in cloud settings. The study underscores the need for time-resolved hardware-performance data and transparent transpilation details to interpret cloud QC results and guide platform selection.

Abstract

Quantum computing represents a radical departure from conventional approaches to information processing, offering the potential for solving problems that can never be approached classically. While large scale quantum computer hardware is still in development, several quantum computing systems have recently become available as commercial cloud services. We compare the performance of these systems on several simple quantum circuits and algorithms, and examine component performance in the context of each system's architecture.

Figures (10)

• Figure 1: Quantum computer cores available on the cloud. Left: Ion trap quantum computer chip from IonQ. Qubits are stored in electronic states of individual atoms (ions), shown glowing when laser light is applied. The ions are electromagnetically confined above a silicon chip (fabricated at Sandia National Laboratories), and qubit initialization, gates, and readout are realized with laser beams. Right: Sample superconducting quantum computer chip from IBM. Qubits are represented by individual superconducting circuits, connected with electrical wiring on a 2D lattice. (Photos courtesy of IonQ and IBM.)
• Figure 2: Quantum gates native to various quantum computing architectures. Shown for each operation is the evolution of the qubit states (above) and the block circuit diagram with time going left to right (below). (a) The single-qubit rotation gate $R(\theta,\phi)$ creates superpositions according to two continuous parameters $\theta$ and $\phi$. (b) The $CZ$ operation on Rigetti systems performs a $Z$ rotation on a target qubit depending on a control qubit. (c) The $XX$ gate on IonQ systems and (d) the $ZX$ gate implemented in IBM superconducting systems both operate on two qubits with continuous parameter $\chi$ set to $\pi/4$.
• Figure 3: Topology of qubit connectivity on the quantum computers used in this paper. Circles represent qubits, and lines represent the available two-qubit gates between qubits. (a) Rigetti Aspen-8 (31 qubits), (b) IBM-Melbourne (15 qubits), and (c) IBM-Vigo (5 qubits) superconducting quantum computers. (d) IonQ (11-qubit) ion trap quantum computer.
• Figure 4: Standard universal quantum gates. The two single-qubit gates in this family are the Hadamard gate (left) and T gate (middle). The two-qubit CNOT gate (right) flips the second qubit if and only if the first qubit is in state $\ket{1}$.
• Figure 5: Circuit for testing two-qubit gate error accumulation in the IBM-Melbourne system. The boxed portion of the circuit is repeated a number of times. Note that only the upper qubit is measured.