Hybrid CMOS/Memristor Circuit Design Methodology

TL;DR

This work demonstrates with examples an end-to-end design flow for RRAM-based electronics, from the introduction of a custom RRAM model into the authors' chosen CAD tool to performing layout-versus-schematic and post-layout checks including the RRAM device.

Abstract

RRAM technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate with examples an end-to-end design flow for RRAM-based electronics, from the introduction of a custom RRAM model into our chosen CAD tool to performing layout-versus-schematic and post-layout checks including the RRAM device. We envisage that this step-by-step guide to introducing RRAM into the standard integrated circuit design flow will be a useful reference document for both device developers who wish to benchmark their technologies and circuit designers who wish to experiment with RRAM-enhanced systems.

Figures (30)

• Figure 1: Photo of a crosspoint sub-1$\mu$m$^\text{2}$ active area of a single device (top). Example of possible back-end-of-line (BEOL) integration on a standard CMOS process. The simplicity of the multi-layer structure allows for straightforward post-CMOS integration (bottom left and right). One of the terminals of the device is the biasing electrode used to program the device while the other is connected to the CMOS drain. Toggling the gates of the transistor effectively acts as a selector for that specified device.
• Figure 2: Switching surface based on the model used for this work (reproduced from Messaris_2018). RS in this context stands for "resistive state".
• Figure 3: Analogue switching (top) of a Pt/Al$_\text{2}$O$_\text{3}$/TiO$_\text{2}$/Pt RRAM device with respect to an applied stimulus (bottom). Read-outs (ie. samplings of the resistive state) are interspersed between programming phases. The modelled stimulus for the same input is noted with a solid coloured line (top). A number of 500 programming pulses were used to elicit this kind of response from the device. A set of 100 reading pulses was added between programming phases to assert stability of the current resistive state.
• Figure 4: Behavioural model response based on the response of the device shown in fig. \ref{['fig:fitted']}. (top) Dependence of the modelled response on applied pulse width for constant amplitude pulses and (bottom) for programming voltage ramps. Batches of 10 programming and read-out pulses were used throughout. Traces (a, c) indicate the response of the modelled device for two different input waveforms (b, d) at three different pulse widths (1, 10 and 100 $\mu$s).
• Figure 5: Design Flow for analogue and mixed-signal systems. The design flow is divided into two parts: electrical and physical designs, while the model integration is in blue block.