Ultra-low power on-chip learning of speech commands with phase-change memories

TL;DR

This work demonstrates the ultra-low-power on-chip training and inference of speech commands using Raven, a proposed NVIMC-based neuromorphic accelerator using the phase change memories (PCMs), which it is shown can be trained on- chip with power consumption as low as 30~uW, suitable for edge applications.

Abstract

Embedding artificial intelligence at the edge (edge-AI) is an elegant solution to tackle the power and latency issues in the rapidly expanding Internet of Things. As edge devices typically spend most of their time in sleep mode and only wake-up infrequently to collect and process sensor data, non-volatile in-memory computing (NVIMC) is a promising approach to design the next generation of edge-AI devices. Recently, we proposed an NVIMC-based neuromorphic accelerator using the phase change memories (PCMs), which we call as Raven. In this work, we demonstrate the ultra-low-power on-chip training and inference of speech commands using Raven. We showed that Raven can be trained on-chip with power consumption as low as 30~uW, which is suitable for edge applications. Furthermore, we showed that at iso-accuracies, Raven needs 70.36x and 269.23x less number of computations to be performed than a deep neural network (DNN) during inference and training, respectively. Owing to such low power and computational requirements, Raven provides a promising pathway towards ultra-low-power training and inference at the edge.

Figures (10)

• Figure 1: Circuit equivalent of the PCM synapse comprising of two 3T1R circuits Ishii2019. The two variable resistors, $R_{p}$ and $R_{n}$ are designed using the non-volatile PCMs. The synaptic weight is stored as the difference of analog conductance between $R_{p}$ and $R_{n}$. To access the weight electrically, two currents are passed through the $R_{p}$ and $R_{n}$ from current mirror circuit. The difference of the flowing current are sensed in the current mirror circuit by charging and discharging a capacitor in neurons. The voltage drop/gain on the capacitor indicates the magnitude and sign of the synaptic weight. Note that synaptic weight should be defined as conductance ($\it{G}$) rather than resistance ($\it{R}$). However, for convenience, we define the synaptic weight in terms of $\it{R}$ in this work.
• Figure 2: Circuit operation of the PCM-based synapse in the presence of pre and postsynaptic neurons Ishii2019. (a) when spikes propagate from pre to the postsynaptic neuron. If the potential of postsynaptic neuron exceeds the threshold, spikes with predefined pulse timing (b) will be generated.
• Figure 3: Circuit operation of PCM-based synapse in the presence of pre and postsynaptic neurons Ishii2019. (a) when spikes propagate from post to the presynaptic neuron. If the potential of presynaptic neuron exceeds the threshold, spikes with predefined pulse timing (b) will be fired.
• Figure 4: (a) the circuit operation during the STDP-based weight update, and the timing diagrams of spikes needed to (b) increase or (c) decrease the weight Ishii2019.
• Figure 5: The schematic of PCM-based synaptic array connected presynaptic neurons in the left and postsynaptic neurons at the bottom Ishii2019, which we call as Raven.