GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning

TL;DR

This work introduces GCN-RL Circuit Designer, a topology-aware, transferable approach to automatic transistor sizing. It combines a Graph Convolutional Network with a continuous-action actor-critic RL agent to open the circuit optimization loop and learn sizing policies that transfer across technology nodes and circuit topologies. The method demonstrates superior Figure of Merit (FoM) on four real-world circuits and enables knowledge transfer across nodes (e.g., 180 nm to 45 nm) and topologies (Two-TIA to Three-TIA) with limited additional training. By embedding circuit topology into the learning process and enabling cross-domain policy reuse, GCN-RL accelerates design porting and reduces simulation costs in analog circuit design.

Abstract

Automatic transistor sizing is a challenging problem in circuit design due to the large design space, complex performance trade-offs, and fast technological advancements. Although there has been plenty of work on transistor sizing targeting on one circuit, limited research has been done on transferring the knowledge from one circuit to another to reduce the re-design overhead. In this paper, we present GCN-RL Circuit Designer, leveraging reinforcement learning (RL) to transfer the knowledge between different technology nodes and topologies. Moreover, inspired by the simple fact that circuit is a graph, we learn on the circuit topology representation with graph convolutional neural networks (GCN). The GCN-RL agent extracts features of the topology graph whose vertices are transistors, edges are wires. Our learning-based optimization consistently achieves the highest Figures of Merit (FoM) on four different circuits compared with conventional black-box optimization methods (Bayesian Optimization, Evolutionary Algorithms), random search, and human expert designs. Experiments on transfer learning between five technology nodes and two circuit topologies demonstrate that RL with transfer learning can achieve much higher FoMs than methods without knowledge transfer. Our transferable optimization method makes transistor sizing and design porting more effective and efficient.

Figures (8)

• Figure 1: Graph Convolutional Neural Networks based Reinforcement Learning for Automatic Transistor Sizing.
• Figure 2: GCN-RL Overview: Six steps in one optimization iteration: (1) Embed topology. (2) Generate graph and node states. (3) Generate actions (circuit parameters). (4) Refine circuit parameters. (5) Evaluate circuit parameters. (6) Update RL policy with the reward.
• Figure 3: Reinforcement learning agent with multi-layer GCN.
• Figure 4: Our RL agent can transfer design knowledge by inheriting the pretrained weights of the actor-critic model. Human need use heuristic based methods to re-design the parameters. BO and ES cannot transfer.
• Figure 5: Learning curves of different algorithms. The proposed GCN-RL achieves the highest FoM in four baselines.