Next-Generation Topology of D-Wave Quantum Processors

TL;DR

The paper introduces D-Wave's Pegasus topology as a higher-connectivity successor to Chimera, detailing its formal description, embedding strategies, and potential for error correction. It demonstrates substantial improvements in embedding efficiency—roughly 50–60% shorter chains for key graphs—and outlines how odd couplers enable simple energy-scale amplification for logical qubits. Comparative analyses reveal Pegasus shifts the balance of Ising-model behavior, with higher ferromagnetic transition temperatures and altered spin-glass dynamics, and show some classical TTS methods are less effective on Pegasus than on Chimera. Overall, Pegasus expands embedding capabilities and offers a versatile platform for exploring quantum annealing performance on structured problems.

Abstract

This paper presents an overview of the topology of D-Wave's next-generation quantum processors. It provides examples of minor embeddings and discusses performance of embedding algorithms for the new topology compared to the existing Chimera topology. It also presents some initial performance results for simple, standard Ising model classes of problems.

Figures (12)

• Figure 1: Roadway-style drawing of qubits (dots) and couplers (lines) in a $P_3$-sized Pegasus(0) processor, where curved blue lines are “internal” couplers, long red lines are “external” couplers, and short red lines are “odd” couplers.
• Figure 2: Straight-line drawing of qubits (dots) and couplers (lines) in a $P_3$-sized Pegasus(0) processor, where blue lines are “internal” couplers, long red lines are “external” couplers, and short red lines are “odd” couplers.
• Figure 3: Coordinates of vertical qubits in a Pegasus $P_3$ processor.
• Figure 4: Coordinates of horizontal qubits in a Pegasus $P_3$ processor.
• Figure 5: Embedding of $K_{62}$ in $P_6$. See Section \ref{['sec:embclique']}