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Generalized Data Placement Strategies for Racetrack Memories

Asif Ali Khan, Andres Goens, Fazal Hameed, Jeronimo Castrillon

TL;DR

This work tackles the shift overhead in ultra-dense racetrack memories by proposing generalized, timing- and liveliness-aware data placement strategies. It introduces a fast sequence-aware inter-DBC distribution and a GA-based framework for joint inter- and intra-DBC optimization to reduce RTM shifts across architectures and varying numbers of DBCs. Empirical results show sizable gains: approximately 4.3× fewer shifts on average, around 46% faster latency, and about 55% lower energy compared to the prior state-of-the-art, with GA solutions approaching near-optimal performance. The methods are architecture-agnostic and can complement existing intra-DBC heuristics, offering practical impact for RTM-based memory hierarchies and energy-efficient designs.

Abstract

Ultra-dense non-volatile racetrack memories (RTMs) have been investigated at various levels in the memory hierarchy for improved performance and reduced energy consumption. However, the innate shift operations in RTMs hinder their applicability to replace low-latency on-chip memories. Recent research has demonstrated that intelligent placement of memory objects in RTMs can significantly reduce the amount of shifts with no hardware overhead, albeit for specific system setups. However, existing placement strategies may lead to sub-optimal performance when applied to different architectures. In this paper we look at generalized data placement mechanisms that improve upon existing ones by taking into account the underlying memory architecture and the timing and liveliness information of memory objects. We propose a novel heuristic and a formulation using genetic algorithms that optimize key performance parameters. We show that, on average, our generalized approach improves the number of shifts, performance and energy consumption by 4.3x, 46% and 55% respectively compared to the state-of-the-art.

Generalized Data Placement Strategies for Racetrack Memories

TL;DR

This work tackles the shift overhead in ultra-dense racetrack memories by proposing generalized, timing- and liveliness-aware data placement strategies. It introduces a fast sequence-aware inter-DBC distribution and a GA-based framework for joint inter- and intra-DBC optimization to reduce RTM shifts across architectures and varying numbers of DBCs. Empirical results show sizable gains: approximately 4.3× fewer shifts on average, around 46% faster latency, and about 55% lower energy compared to the prior state-of-the-art, with GA solutions approaching near-optimal performance. The methods are architecture-agnostic and can complement existing intra-DBC heuristics, offering practical impact for RTM-based memory hierarchies and energy-efficient designs.

Abstract

Ultra-dense non-volatile racetrack memories (RTMs) have been investigated at various levels in the memory hierarchy for improved performance and reduced energy consumption. However, the innate shift operations in RTMs hinder their applicability to replace low-latency on-chip memories. Recent research has demonstrated that intelligent placement of memory objects in RTMs can significantly reduce the amount of shifts with no hardware overhead, albeit for specific system setups. However, existing placement strategies may lead to sub-optimal performance when applied to different architectures. In this paper we look at generalized data placement mechanisms that improve upon existing ones by taking into account the underlying memory architecture and the timing and liveliness information of memory objects. We propose a novel heuristic and a formulation using genetic algorithms that optimize key performance parameters. We show that, on average, our generalized approach improves the number of shifts, performance and energy consumption by 4.3x, 46% and 55% respectively compared to the state-of-the-art.

Paper Structure

This paper contains 14 sections, 1 equation, 6 figures, 1 table, 1 algorithm.

Table of Contents

  1. Introduction
  2. Background
  3. RTM architecture
  4. State-of-the-art data placement in RTMs
  5. Generalized data placement in RTM
  6. Baseline inter-DBC placement
  7. Sequence-aware inter-DBC distribution
  8. Genetic algorithms for data placement in RTM
  9. Evaluation
  10. Experimental setup
  11. Analysis of heuristics: Reduction in shifts
  12. Overall performance and energy analysis
  13. Related work
  14. Conclusions and outlook

Figures (6)

  • Figure 1: RTM cell structure (red and blue dots on the nanowire represent upward and downward magnetization directions respectively)
  • Figure 2: RTM architecture
  • Figure 3: Example showing (a) Variable set (b) Access sequence and the time of occurrence of each access (c) AFD placement Chen2016 (d) Sequence-aware placement (e) Timing and access frequency of each variable
  • Figure 4: Shifts improvement in our proposed solutions for various RTM configurations
  • Figure 5: Overall energy consumption normalized to the baseline AFD-OFU
  • ...and 1 more figures