A Novel Visual Fault Detection and Classification System for Semiconductor Manufacturing Using Stacked Hybrid Convolutional Neural Networks

TL;DR

The paper addresses automated visual fault inspection in semiconductor manufacturing to detect and classify defects early, aiming to improve yield and reduce costs. It introduces a stacked hybrid CNN (SH-CNN) that combines classical image-processing localization with deep CNNs to enable ROI-focused processing at multiple detail levels. The main contributions include a multi-stage pipeline with chip and street localization, a VGG-inspired CNN architecture, and extensive evaluation showing SH-CNN outperforms traditional learning-based inspectors. The work has practical significance for reducing production losses and can be extended with sensor data fusion and deployment under real manufacturing conditions.

Abstract

Automated visual inspection in the semiconductor industry aims to detect and classify manufacturing defects utilizing modern image processing techniques. While an earliest possible detection of defect patterns allows quality control and automation of manufacturing chains, manufacturers benefit from an increased yield and reduced manufacturing costs. Since classical image processing systems are limited in their ability to detect novel defect patterns, and machine learning approaches often involve a tremendous amount of computational effort, this contribution introduces a novel deep neural network based hybrid approach. Unlike classical deep neural networks, a multi-stage system allows the detection and classification of the finest structures in pixel size within high-resolution imagery. Consisting of stacked hybrid convolutional neural networks (SH-CNN) and inspired by current approaches of visual attention, the realized system draws the focus over the level of detail from its structures to more task-relevant areas of interest. The results of our test environment show that the SH-CNN outperforms current approaches of learning-based automated visual inspection, whereas a distinction depending on the level of detail enables the elimination of defect patterns in earlier stages of the manufacturing process.

Figures (4)

• Figure 1: Wafer overview with chip and street segments.
• Figure 2: Processing steps control flow graph of localization, augmentation, and classification with switches S1 and S2.
• Figure 3: Designed visual fault inspection system for chip and street localization, augmentation, and classification. Chip and street processing each undergo one iteration of the control flow graph shown in Fig. \ref{['figure:processing_steps']}.
• Figure 4: Street and chip classification ground truth visualized for flawless (•), anomaly (•), and faulty (•) streets and chips.