Electronics Development for the New Photo-Detectors (PDOM and D-Egg) for IceCube-Upgrade

TL;DR

This work addresses the electronics development for IceCube-Upgrade optical sensors, focusing on unifying the front-end electronics of PDOM and D-Egg to a common architecture capable of continuous PMT waveform digitization and surface data transmission. It describes a hardware stack comprising a 14-bit, 250 MSPS ADC on the mainboard, FPGA-based processing, and an STM32H743 MCU with an IceCube Communication Module (ICM) to deliver data in a common format to surface DAQ. Prototyping results from the D-Egg mainboard show successful noise mitigation and initial power-test outcomes, with ongoing FPGA/MCU performance validation and parallel PDOM development. The work aims to reduce maintenance effort, streamline software, and enhance timing, calibration, and data integrity for IceCube-Upgrade.

Abstract

The planned IceCube-Upgrade will enhance the capability of IceCube in the detection of GeV-scale neutrino physics and enable an improved measurement of the properties of the glacial ice. Three types of new optical sensors will be deployed during the Upgrade: PDOM, D-Egg, and mDOM. Since the design of the PDOM and D-Egg are very similar, the development of the front-end electronics for the two optical sensors has been merged. The photo-electron signals detected by the PMTs are digitized with high-speed ultra-low power ADCs and processed in an FPGA, before being sent to the data acquisition system located on the surface of the South-Pole glacier. The almost final revision of the front-end electronics is equipped with the common microcontroller unit and the communication daughter board for simplifying the communication scheme for the three different modules. This contribution focuses on the design of the front-end electronics and presents first results from the performance tests.

Figures (5)

• Figure 1: IceCube DOM and PDOM PDOM
• Figure 2: D-Egg glass
• Figure 4: Simple block diagram for the PDOM/D-Egg mainboard. The upper PMT system is only for the D-Egg. The mainboard contains an FPGA, a microcontroller unit (MCU) as the processor, and the separated board "IceCube Communication Module" (ICM). ICM receives commands from the surface, generates commands to the FPGA and the MCU, and sends collected data to the surface DAQ system. The MCU drives the operation software. The FPGA receives digitized data from the ADC and sends them to ICM. The board power is supplied by the surface system, and the voltage is stepped down to 5 V to supply voltage to the mainboard components.
• Figure 5: Analog front-end circuit. An amplifier generates a differential signal. The proper baseline offset is added before the ADC to keep the information of the undershoot of the waveform. The offset value is controlled by the FPGA.
• Figure 6: Photos of the top side (left) and bottom side (right) of the D-Egg mainboard prototype.